Alacritech - Patents & Licensing

Home > Company > Patents & Licensing

Patents

Alacritech has 38 issued U.S. patents, and numerous other US and international applications are pending. Highlighted below are examples of Alacritech's issued U.S. patent claims. Alacritech maintains an Intellectual Property Licensing Group responsible for IP Licensing.

Further information on Alacritech's patents and published applications can be found by following the links in this page or searching the United States Patent and Trademark Office web site.

1. U.S. Pat. No. 6,226,680 Intelligent network interface system method for protocol processing

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the IMC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

2. U.S. Pat. No. 6,247,060 Passing a communication control block from host to a local device such that a message is processed on the device

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

3. U.S. Pat. No. 6,334,153 Passing a communication control block from host to a local device such that a message is processed on the device

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

4. U.S. Pat. No. 6,389,479 Intelligent network interface device and system for accelerated communication

5. U.S. Pat. No. 6,393,487 Passing a communication control block to a local device such that a message is processed on the device

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

6. U.S. Pat. No. 6,427,171 Protocol processing stack for use with intelligent network interface device

A host CPU runs a network protocol processing stack that provides instructions not only to process network messages but also to allocate processing of certain network messages to a specialized network communication device, offloading some of the most time consuming protocol processing from the host CPU to the network communication device. By allocating common and time consuming network processes to the device, while retaining the ability to handle less time intensive and more varied processing on the host stack, the network communication device can be relatively simple and cost effective. The host CPU, operating according to instructions from the stack, and the network communication device together determine whether and to what extent a given message is processed by the host CPU or by the network communication device.

7. U.S. Pat. No. 6,427,173 Intelligent network interfaced device and system for accelerated communication

An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host.

8. U.S. Pat. No. 6,434,620 TCP/IP offload network interface device

9. U.S. Pat. No. 6,470,415 Queue system involving SRAM head, SRAM tail and DRAM body

A device for queuing information combines the speed of SRAM with the low cost and low power consumption of DRAM, affording substantial expansion of high-speed data storage in queues without corresponding increases in costs. The queues have a variable size, and provide fast, flexible and efficient data storage via an SRAM interface and a DRAM body. The queues may hold pointers to buffer addresses or other data that allow manipulation of information in the buffers via manipulation of the queues. Particular utility for this mechanism exists in situations for which high-speed access to queues is beneficial, flexible queue size is advantageous, and/or the smaller size and lower cost of DRAM compared to SRAM is of value.

10. U.S. Pat. No. 6,591,302 Queue system involving SRAM head, SRAM tail and DRAM body

A network interface device provides a fast-path that avoids most host TCP and IP protocol processing for most messages. The host retains a fallback slow-path processing capability. In one embodiment, generation of a response to a TCP/IP packet received onto the network interface device is accelerated by determining the TCP and IP source and destination information from the incoming packet, retrieving an appropriate template header, using a finite state machine to fill in the TCP and IP fields in the template header without sequential TCP and IP protocol processing, combining the filled-in template header with a data payload to form a packet, and then outputting the packet from the network interface device by pushing a pointer to the packet onto a transmit queue. A transmit sequencer retrieves the pointer from the transmit queue and causes the corresponding packet to be output from the network interface device.

11. U.S. Pat. No. 6,658,480 Intelligent network interface system and method for accelerated protocol processing

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The CPD provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The CPD also assists the host CPU for those message packets that are chosen for processing by host software layers. A context for a message is defined that allows DMA controllers of the CPD to move data, free of headers, directly to or from a destination or source in the host. The context can be stored as a communication control block (CCB) that is controlled by either the CPD or by the host CPU. The CPD contains specialized hardware circuits that process media access control, network and transport layer headers of a packet received from the network, saving the host CPU from that processing for fast-path messages.

12. U.S. Pat. No. 6,687,758 Intelligent network interface system method for protocol processing

At least one intelligent network interface card (INIC) is coupled to a host computer to offload protocol processing for multiple network connections, reducing the protocol processing of the host. Plural network connections can maintain, via plural INIC ports and a port aggregation switch, an aggregate connection with a network node, increasing bandwidth and reliability for that aggregate connection. Mechanisms are provided for managing this aggregate connection, including determining which port to employ for each individual network connection, and migrating control of an individual network connection from a first INIC to a second INIC.

13. U.S. Pat. No. 6,697,868 Protocol processing stack for use with intelligent network interface device

14. U.S. Pat. No. 6,751,665 Providing window updates from a computer to a network interface device

15. U.S. Pat. No. 6,757,746 Obtaining a destination address so that a network interface device can write network data without headers directly into host memory

A Network Interface device (NI device) coupled to a host computer receives a multi-packet message from a network (for example, the Internet) and DMAs the data portions of the various packets directly into a destination in application memory on the host computer. The address of the destination is determined by supplying a first part of the first packet to an application program such that the application program returns the address of the destination. The address is supplied by the host computer to the NI device so that the NI device can DMA the data portions of the various packets directly into the destination. In some embodiments the NI device is an expansion card added to the host computer, whereas in other embodiments the NI device is a part of the host computer.

16. U.S. Pat. No. 6,807,581 Intelligent network storage interface system

An interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host. The interface device includes hardware circuitry for processing network packet headers, and can use a dedicated fast-path for data transfer between the network and the storage unit, the fast-path set up by the host. The host CPU and protocol stack avoids protocol processing for data transfer over the fast-path, freeing host bus bandwidth, and the data need not cross the I/O bus, freeing I/O bus bandwidth. The storage unit may include RAID or other multiple drive configurations and may be connected to the INIC by a parallel channel such as SCSI or by a serial channel such as Ethernet or Fibre Channel. The interface device contains a file cache that stores data transferred between the network and storage unit, with organization of data in the interface device file cache controlled by a file system on the host. Additional interface devices may be connected to the host via the I/O bus, with each additional interface device having a file cache controlled by the host file system, and providing additional network connections and/or being connected to additional storage units.

17. U.S. Pat. No. 6,938,092 TCP offload device that load balances and fails-over between aggregated ports having different MAC addresses

TCP/IP traffic passing over a TCP connection is initially load balanced by a TCP offload network interface device (NID) in fast-path between multiple ports of an aggregation team. A failure then occurs on one of the ports. Processing of the TCP connection then switches to slow-path. The function of the failed port is then assumed by another functioning port of the team such that fast-path processing of the TCP connection by the TCP offload NID automatically resumes. The two ports of the TCP offload NID (the failed port and the port that assumes its functionality) use different MAC addresses. Fast-path load balancing and fail-over are therefore possible without the use of a Fast-Etherchannel switch that would have required the two ports to use the same MAC address.

18. U.S. Pat. No. 6,941,386 Protocol processing stack for use with intelligent network interface device

19. U.S. Pat. No. 6,965,941 Transmit fast-path processing on TCP/IP offload network interface device

20. U.S. Pat. No. 6,996,070 U.S. Pat. No. 6,996,070 TCP/IP offload device with reduced sequential processing

A TCP Offload Engine (TOE) device includes a state machine that performs TCP/IP protocol processing operations in parallel. In a first aspect, the state machine includes a first memory, a second memory, and combinatorial logic. The first memory stores and simultaneously outputs multiple TCP state variables. The second memory stores and simultaneously outputs multiple header values. In contrast to a sequential processor technique, the combinatorial logic generates a flush detect signal from the TCP state variables and header values without performing sequential processor instructions or sequential memory accesses. In a second aspect, a TOE includes a state machine that performs an update of multiple TCP state variables in a TCB buffer all simultaneously, thereby avoiding multiple sequential writes to the TCB buffer memory. In a third aspect, a TOE involves a state machine that sets up a DMA move in a single state machine clock cycle.

21. U.S. Pat. No. 7,042,898 Reducing delays associated with inserting a checksum into a network message

A first partial checksum for the header portion of a TCP header is generated on an intelligent network interface card (INIC) before all the data of the data payload of the TCP message has been transferred to the INIC. A pseudopacket with the first partial checksum and the data is assembled in DRAM on the INIC as the data arrives onto the INIC. When the last portion of the data of the data payload is received onto the INIC, a second partial checksum for the data payload is generated. The pseudopacket is read out of DRAM for transfer to a network. While the pseudopacket is being transferred, the second partial header is combined with the first partial header and the resulting final checksum is inserted into the pseudopacket so that a complete TCP packet with a correct checksum is output from the INIC to the network.

22. U.S. Pat. No. 7,076,568 Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket

23. U.S. Pat. No. 7,089,326 Fast-path processing for receiving data on TCP connection offload devices

24. U.S. Pat. No. 7,093,099 Reducing delays associated with inserting a checksum into a network message

A processor natively executes lookup instructions. The lookup instruction is decoded to determine which general-purpose register (GPR) contains a pointer to a lookup key in a buffer. A variable-length key is read from the buffer and hashed to generate an index into a first-level cache and a hashed tag. An address of a bucket of entries for the index is generated and tags from these entries are read and compared to the hashed tag. When an entry matches the hashed tag, a second-level entry is read. A stored key from the second-level entry is compared to the input key to determine a match. The addresses of the matching second-level and first-level entries are written to GPR's specified by operands decoded from the lookup instruction. When the key or entry data is long, the second-level entry also contains a pointer to a key extension or data extension in a third-level cache.

25. U.S. Pat. No. 7,124,205 Network interface device that fast-path processes solicited session layer read commands

A network interface device connected to a host provides hardware and processing mechanisms for accelerating data transfers between the host and a network. Some data transfers are processed using a dedicated fast-path whereby the protocol stack of the host performs no network layer or transport layer processing. Other data transfers are, however, handled in a slow-path by the host protocol stack. In one embodiment, the host protocol stack has an ISCSI layer, but a response to a solicited ISCSI read request command is nevertheless processed by the network interface device in fast-path. In another embodiment, an initial portion of a response to a solicited command is handled using the dedicated fast-path and then after an error condidtion occurs a subsequent portion of the response is handled using the the slow-path. The interface device uses a command status message to communicate status to the host.

26. U.S. Pat. No. 7,133,940 Network interface device employing a DMA command queue

A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple DMA commands before the processor takes a particular software branch. The processor issues the DMA commands by placing the DMA commands in a memory and then pushing values indicative of the DMA commands onto a DMA command queue. The values are popped off the DMA command queue and are executed by the DMA controller one at a time. The DMA commands are executed in the same order that they were issued by the processor. The processor need not monitor multiple DMA commands to make sure they have all been completed before the software branch is taken, but rather the processor pops a DMA command complete queue to make sure that the last of the DMA commands has been completed.

27. U.S. Pat. No. 7,167,926 TCP/IP offload network interface device

28. U.S. Pat. No. 7,167,927 TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism

A network interface device has a fast-path ACK generating and transmitting mechanism. ACKs are generated using a finite state machine (FSM). The FSM retrieves a template header and fills in TCP and IP fields in the template. The FSM is not a stack, but rather fills in the TCP and IP fields without performing transport layer processing and network layer processing sequentially as separate tasks. The filled-in template is placed into a buffer and a pointer to the buffer is pushed onto a high-priority transmit queue. Pointers for ordinary data packets are pushed onto a low-priority transmit queue. A transmit sequencer outputs a packet by popping a transmit queue, obtaining a pointer, and causing information pointed to by the pointer to be output from the network interface device as a packet. The sequencer pops the high-priority queue in preference to the low-priority queue, thereby accelerating ACK generation and transmission.

29. U.S. Pat. No. 7,174,393 TCP/IP offload network interface device

A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The TONID also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the TONID to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the TONID as a communication control block (CCB) that can be passed back to the host for message processing by the host. The TONID contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

30. U.S. Pat. No. 7,185,266 Network interface device for error detection using partial CRCS of variable length message portions

A device and method are disclosed for calculating a CRC on a message or block of data that has been divided into portions, by calculating a partial CRC corresponding to each of the portions and then combining the partial CRCs. The device and method are operable for portions that may have different lengths, and which may be received out of order.

31. U.S. Pat. No. 7,191,241 Fast-path apparatus for receiving data corresponding to a TCP connection

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

32. U.S. Pat. No. 7,191,318 Native copy instruction for file-access processor with copy-rule-based validation

A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and execution buffers, DRAM, SRAM, and other memory. A copy-with-validate instruction has an operand pointing to a first rule in an immediate rule table. The first rule controls validation of a first data-item in the data being copied. Validation includes range and equality checking of the data-item. The value of the data-item or the current offset can be written to a register. A format field in the rule indicates the size of the data-item, or the size is read from the data-item for variable-size formats. The current offset is incremented by the size. The next data-item is validated by a next rule, and other rules in the immediate table control validation of other data-items in the data block.

33. U.S. Pat. No. 7,237,036 Fast-path apparatus for receiving data corresponding a TCP connection

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

34. U.S. Pat. No. 7,254,696 Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests

A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands. The FLIC engine is optimized to parse, lookup, and process long strings common in content-service requests and can offload file-server requests by looking up meta-data and pointers.

35. U.S. Pat. No. 7,284,070 Intelligent network interface system method for protocol processing

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

36. U.S. Pat. No.7,337,241 Fast-path apparatus for receiving data corresponding to a TCP connection

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

37. U.S. Pat. No. 7,461,160 Intelligent network interface system method for protocol processing

38. U.S. Pat. No. 7,472,156 Transferring control of a TCP connection between devices

A system and method for network communication, comprising a device coupled between a computer and a network to receive from the computer a Transport Control Protocol (TCP) connection, the device receiving from the network at least one packet associated with the TCP connection and processing a TCP header for the at least one packet, the computer having a memory storing instructions to pass the TCP connection to the device in first and second commands, the first command signaling an intent to transfer of the TCP connection, the second command responsive to an indication from the device that the device is prepared to receive the TCP connection.